The disclosed embodiments of the present invention relate to forwarding packets, and more particularly, to a multi-level replication counter storage device for multicast packet processing and related method for managing multicast packet processing.
A network switch is a computer networking device that links different electronic devices. For example, the network switch receives an incoming packet generated from a source electronic device connected to it, and transmits an outgoing packet derived from the received packet only to one or more destination electronic devices for which the received packet is meant to be received. In general, the network switch has a packet buffer for buffering packet data of packets received from ingress ports, and forwards the packets stored in the packet buffer through egress ports. If the same packet is requested by a group of destination electronic devices connected to different egress ports of the network switch, a requested packet, also known as a multicast packet, is obtained in a single transmission from a source electronic device connected to one ingress port of the network device, and a multicast operation is performed by the network switch to deliver/broadcast copies of the requested packet stored in the packet buffer to the group of destination electronic device. A replication counter (or called as multicast counter) is commonly used by the network switch to count the number of multicast or broadcast targets in a network.
In one conventional design, a counter storage device is realized by a memory device only. Hence, when an en-queue operation is performed upon the memory device, an initial count value is stored into the memory. When a de-queue operation is performed upon the memory device, a stored count value is read from a memory location, decreased by one, and then written back to the same memory location. In general, the memory device needs several clock cycles to finish one de-queue operation. Besides, most memory devices only allow read or write at one time. Therefore, if the en-queue or de-queue rate is high (i.e., the switch device is used in a high-speed network), the operating frequency of the memory device cannot meet the bandwidth requirement.
In another conventional design, a counter storage device is realized by a flip-flop array only. Each flip-flop in the flip-flop array is capable of finishing one de-queue operation (which directly updates a stored count value) in a single clock cycle. Hence, if the en-queue or de-queue rate is high (i.e., the switch device is used in a high-speed network), the operating frequency of the flip-flop array is able to meet the bandwidth requirement. However, the area of the flip-flop array is usually 8-12 times as large as that of the memory device if there is the same size of m-words by n-bits. As a result, the cost is high when the counter storage device is implemented using the flip-flop array.
Thus, there is a need for an innovative replication counter storage design which can meet the bandwidth requirement with acceptable area and cost.